FIG. 6 shows a prior art semiconductor memory device. In FIG. 6 only necessary portions are illustrated for simplification. In FIG. 6, the reference numerals 1 and 2 designate transistors constituting a current switch for switching a current in accordance with the voltage of an address signal V IN which is from the previous stage. The reference character V BB designates a reference voltage, and this is set at an intermediate voltage in the range of the voltage swing V IN. The reference numeral 4 designates a resistor, and the reference numeral 8 designates a current source. The reference numeral 3 designates a transistor for driving word line 5. This transistor 3 makes the voltage of word line 5 low or high in accordance with the voltage V IN being high or low. The numeral 7 designates a Schottky barrier diode (hereinafter referred to as "SBD") clamping memory cell. A plurality of memory cells are connected to each word line, and the memory cells include two multi-emitter transistors 75 and 76. An inverter is cconstructed with the multi-emitter transistors and the collector load consists of a load resistor (71 or 72) connected in parallel with an SBD (73 or 74). The memory cells consist of flip-flops characterised by two cross-coupled inverters. Stored data in the memory cells are discriminated by voltage differences between nodes N1 and N2, and the voltage difference is referred to as memory cell voltage swing. The reference numeral 6 designates a drain line. In order to hold the stored data, this drain line 6 is connected to a current source (not shown) so that a current (current value IH) is always taken out from each memory cell. The reference character V CC designates a power supply voltage.
The device will be operated as follows.
When the address output signal voltage V IN is higher than the reference voltage V BB, the transistor 1 is turned on, and the base voltage of the word line driving transistor 3 becomes lower than the power supply voltage V CC by the voltage of a product of the current of the current source 8 and the resistance of the resistor 4. The voltage of word line 5 is further lowered by the base emitter voltage V BE of the transistor 3. This state is referred to as a word line non-selected state.
On the other hand, when the address output signal voltage V IN is lower than the reference voltage V BB, the transistor 2 is turned on, and the base voltage of the word line driving transistor 3 rises up to about the power supply voltage V CC. Then, the voltage of the word line 5 is higher than that of the non-selected word line state. This is referred to as a selected word line state. The word line voltage in this state is V CC-V BE.
In the non-selected word line state, the memory cell voltage swing is determined by the following. If it is presumed hhat the transistors 75 and 76 of the memory cell 7 are in an ON and OFF state, respectively, the voltage of the node N2 is equal to that of word line 5. On the contrary, the voltage of the node N1 becomes lower than that of the word line by a value of IH.multidot.RL because almost all the memory holding current IH flows through the load resistance 71. Accordingly, the memory cell voltage swing is IH.multidot.RL.
In the prior art semiconductor memory device with such a construction, the memory cell voltage swing at the non-selected word line state cannot be made larger than a predetermined value, and accordingly the data in the memory is likely to be inverted by induced electron-hole pairs which are generated by .alpha. rays incident to the memory cell.
The likelihood of the inversion of the stored daa due to .alpha. rays is inversely proportional to the memory cell voltage swing. Accordingly, in order to prevent the inversion of the stored data the memory cell voltage swing is to be made large enough but for that purpose the memory holding current or the load resistance of the memory cell must be made large. However, in either case there are the following restrictions.
First of all, the memory data holding current in the memory cell unselected state cannot be made as large because of the restriction in the power consumption. The upper limit is IH=30 to 60 .mu.A for one having a memory capacity of 1K bits, and IH=10 to 15 .mu.A for one having a memory capacity of 4K bit. In the holding current of such a degree, the upper limit of the possible memory cell voltage swing is limited to 0.4 to 0.5 V. Although the load resistances 71 and 72 of the memory cell can be made larger in order to increase the voltage swing, when the voltage swing becomes likely to be larger than 0.4 to 0.5 V the current flowing through the load resistance is decreased because the SBD is turned ON then, and it is impossible to obtain a voltage difference larger than the forward voltage drop of the SBD (0.4 to 0.5 V) in the holding current range above.
On the contrary, in the selected word line state a larger current other than the stored data holding current can be taken out from the memory cell by another current source, whereby a current flowing through the SBD connected to the collector of the ON side transistor of the memory cell is increased, and the forward voltage drop is also increased. It is usual in the state of the art that a larger current is taken out from the word line in the selected state, an increase of the current can be small enough compared to the case in which the data holding current is increased because the increase of the former relates only to one word line, the latter relates to all the word lines. Accordingly, the memory cell voltage swing can be made large, and the inversion rate of the stored data due to .alpha. rays is decreased to a negligible extent with relative to the non-selected state. Accordingly, in order to prevent the inversion of the stored data due to .alpha. rays, it is necessary to increase the memory cell voltage swing at the non-selected word line state.